高性能，基于EEPROM的可编程逻辑器件
(PLDs) based on second-generation MAX® architecture
（PLD）基于第二最大®架构
■ 5.0-V in-system programmability (ISP) through the built-in
■5.0 - V的在系统可编程（ISP）通过内置
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
IEEE 1149.1标准的联合测试行动小组（JTAG）接口可用
MAX 7000S devices
MAX 7000S设备
– ISP circuitry compatible with IEEE Std. 1532
–ISP电路与IEEE 1532标准兼容
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
■包括5.0 - V MAX的7000设备和5.0 - V的ISP MAX 7000S
devices
设备
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S
■内置JTAG边界扫描测试（BST）电路的MAX7000S系列
devices with 128 or more macrocells
128或更多的宏单元设备
■ Complete EPLD family with logic densities ranging from 600 to
完整的家庭■EPLD逻辑密度范围从600到
5,000 usable gates (see Tables 1 and 2)
5000可用门（见表1和2）
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter
■5 ns的引脚到引脚的逻辑延迟到175.4-mhz计数器
frequencies (including interconnect)
频率（包括互连）
■ PCI-compliant devices available
■PCI兼容的设备
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